1. Field of the Invention
The invention relates, in general, to a semiconductor memory device and an operation method of the same, and particularly to a semiconductor memory device having data lines which are provided independently from each other for reading and writing data, respectively, and an operation method of the same.
2. Description of the Prior Art
DRAMs (Dynamic Random Access Memories) have such features that memory capacities can be easily increased, as compared with SRAMs (Static Random Access Memories), but they require a relatively long time for reading and writing data.
Reduction of the access time of DRAMs has been attempted from various aspects. In one aspect, it relies on improvement of components and elements of the DRAM such as advance of performance of transistors in the DRAM and reduction of a signal delay time of interconnections in the DRAM, which are achieved by the advance of the process technology of the semiconductor integrated circuit device. In another aspect, it relies on improvement of circuit constructions of the DRAM achieved by the design technology of the semiconductor integrated circuit device.
The reduction of the access time of the DRAM has been mainly realized from the former aspect. In recent years, however, remarkable reduction of the access time of the DRAM has been attempted from the latter aspect.
The latter attempt is based on a following view. A major cause of preventing the reduction of the access time in the conventional DRAM is that "in a data reading operation, it is impossible to operate a sense amplifier immediately after activation of a word line connected to memory cells from which the data is to be read". This attempt will be described below in detail with reference to FIGS. 7-11.
FIG. 7 is a circuit diagram showing a construction of a major portion of the conventional DRAM to which the above attempt is not applied.
With reference to FIG. 7, a memory cell array block MA includes memory cells MC which are disposed in a row direction and a column direction to form a matrix, word lines WL which are provided correspondingly to rows of the memory cells, respectively, and bit line pairs BL, /BL which are provided correspondingly to columns of the memory cells, respectively.
Each memory cell MC is formed of an N-channel MOS transistor 100 having its gate connected to corresponding word line WL, and a capacitor 200. Transistor 100 and capacitor 200 are mutually connected in series between one of the two bit lines BL and /BL forming the corresponding bit line pair and a cell plate supplying a low potential Vsg.
In the data writing operation and data reading operation, a potential (nearly equal to power supply potential Vcc) at a high level is supplied to one of word lines WL. In all memory cells MC connected to this one word line WL, transistors 100 are turned on, and thus capacitors 200 are electrically connected to corresponding bit lines BL or /BL, respectively.
A sense amplifier SA and a bit line equalizer circuit EQ are connected between two bit lines BL and /BL forming each bit line pair.
Each sense amplifier SA includes two P-channel MOS transistors 300 and 310 connected between two signal lines 360 and 370, and two N-channel MOS transistors 320 and 330 connected between two signal lines 360 and 370. Between signal lines 360 and 370, transistors 300 and 320 are connected in series and also transistors 310 and 330 are connected in series. A connecting point of transistors 300 and 320 is connected to one (BL) of the two bit lines forming the corresponding bit line pair and is also connected to gates of transistors 310 and 330. Similarly, a connecting point of transistors 310 and 330 is connected to the other bit line /BL and gates of transistors 300 and 320.
Accordingly, each sense amplifier SA is activated while signal lines 360 and 370 are receiving supply potential Vcc and ground potential Vss corresponding to the low level, respectively. The activated sense amplifier SA operates as a differential amplifier, which amplifies a potential difference between corresponding two bit lines BL and /BL, and also operates as a temporary memory circuit, which latches the potentials of corresponding two bit lines BL and /BL at the connecting point of transistors 300 and 320 and the connecting point of transistors 310 and 330, respectively.
Each bit line equalizer circuit EQ includes N-channel MOS transistors 400 and 410 which are connected in series between two bit lines BL and /BL forming the corresponding bit line pair. An equalization control signal .phi.EQ is commonly applied to gates of transistors 400 and 410 in all equalizer circuits EQ. In each equalizer circuit EQ, an intermediate potential Vb1 (=Vcc/2) between supply potential Vcc and ground potential Vss is applied to the connecting point of transistors 400 and 410.
In the data writing and reading operations, equalization signal .phi.EQ is at the low level. Thereby, transistors 400 and 410 are turned off in each equalizer circuit EQ, so that intermediate potential Vb1 is not applied to any bit pair BL and /BL. When neither data reading operation nor data writing operation is to be carried out, equalization signal .phi.EQ is at the high level. Thereby, transistors 400 and 410 are turned on in each equalizer circuit EQ, so that each bit lines BL and bit line /BL paired therewith are set equally at the intermediate potential Vb1.
Sense amplifier activation signals .phi.pSA and .phi.nSA are applied to signal lines 360 and 370, respectively. By setting sense amplifier activation signals .phi.pSA and .phi.nSA to have supply potential Vcc and ground potential Vss, respectively, all sense amplifiers SA are activated.
Each bit line BL and bit line /BL paired therewith are connected through N-channel MOS transistors 500 and 510 to data lines /IO and IO, respectively. Transistor 500 connected to bit line BL and transistor 510 connected to bit line /BL paired with bit line BL have gates connected to a common column selecting line CSL. Thus, one column selecting line CSL is provided correspondingly to each bit line pair.
In the data writing and reading operations, the potential at the high level is applied to only one of the column selecting lines CSL. Thereby, both transistors 500 and 510 connected to this one column selecting line CSL are turned on, so that only one bit line pair BL and /BL corresponding to this one column selecting line CSL is electrically connected to data line pair IO and /IO.
Now, a general circuit operation for writing the data will be described below.
In the data writing operation, mutually complementary potentials are externally applied, as write data, to data line pair IO and /IO.
The potentials of data lines IO and /IO are transmitted to transistors 500 and 510 through bit lines corresponding to the one column selecting line to which the potential at the high level is applied (hereinafter referred to as selected bit lines).
The potentials of selected bit lines BL and /BL are latched at nodes N1 and N2 in corresponding sense amplifier SA, respectively.
In memory cell array block MA, if memory cell MC connected to one word line to which the potential at the high level is applied (hereinafter referred to as selected word line) is connected to bit line BL, charging or discharging, which depends on the potential latched in node N1, is caused in capacitor 200 in one memory cell MC connected commonly to selected bit line BL and selected word line WL (hereinafter referred to as selected memory cell).
Meanwhile, if memory cell MC connected to selected word line WL is connected to bit line /BL (one selected bit line), charging or discharging, which depends on the potential latched in node N2, is caused in capacitor 200 in one memory cell MC connected commonly to another selected bit line /BL and the selected word line WL.
Therefore, charging and discharging of capacitor 200 in selected memory cell MC are caused if the write data, i.e., the potential applied to data line IO (if this memory cell is connected to bit line BL) or data line /IO (if this memory cell is connected to bit line /BL) is at the high level and the low level, respectively. The state in which capacitor 200 has been charged and the state in which capacitor 200 has not been charged correspond to data "1" and data "0", respectively.
In this manner, the write data supplied to data line pair IO and /IO is written only in selected one memory cell MC.
In the data reading operation, the data is transmitted from memory cell array MA to data line pair IO and /IO. General circuit operation for reading the data will be described below with reference to FIGS. 7 and 8.
FIG. 8 is a timing chart showing variation of the potentials in some signal lines and some control signals in FIG. 7 in the data reading operation.
When after the fall of bit line equalization signal .phi.EQ (FIG. 8(a)), the potential of one of the word lines WL rises, as shown in FIG. 8(b), to a potential (Vcc+.alpha.) which is slightly higher than the power supply potential Vcc, depending on the stored data in each memory cell MC connected to this word line WL, the potential of bit line BL or /BL connected to this memory cell MC changes.
In a memory cell MC, when transistor 100 is turned on in such conditions that capacitor 200 has been charged, the connecting point between capacitor 200 and transistor 100 has the potential at the high level and bit line BL or /BL connected to this memory cell MC has intermediate potential Vb1, the charge is supplied to this bit line from capacitor 200, so that the potential of this bit line rises from the intermediate potential Vb1. Meanwhile, in a memory cell MC, when transistor 100 is turned on in such conditions that capacitor 200 has not been charged, the connecting point between capacitor 200 and transistor 100 has the potential at the low level and bit line BL or /BL connected to this memory cell MC has the intermediate potential Vb1, the charges flow from the bit line to capacitor 200, so that the potential of this bit line lowers from the intermediate potential Vb1. Since the capacitor 200 has a very small capacity, the potential of the bit line rises and lowers only to a very small extent in the above cases.
In response to the rise of potential of one word line WL, therefore, the potential of each bit line BL (if the memory cell MC connected to this word line WL is connected to bit line BL) or each bit line /BL (if the memory cell MC connected to this word line WL is connected to bit line /BL) slightly rises or lowers from intermediate potential Vb1, as shown in FIG. 8(c), depending on the stored data in one memory cell connected to the selected word line among a plurality of memory cells connected to this bit line. Thereby, a small potential difference is generated between two bit lines BL and /BL forming each bit line pair. Each sense amplifier SA is employed for amplifying the small potential difference between the corresponding bit lines BL and /BL to a value corresponding to the difference between ground potential Vss and supply potential Vcc.
Each sense amplifier SA is activated with a considerable delay after the rise of potential of any word line WL. For this purpose, sense amplifier activation signals .phi.nSA and .phi.nSA are set to the supply potential Vcc and ground potential Vss with a considerable delay after the rise of potential of any word line WL, as shown in FIGS. 8(e) and 8(d). Each sense amplifier SA is inactivated when both sense amplifier activation signals .phi.pSA and .phi.nSA are set to the intermediate potential Vb1.
Owing to the activation of each sense amplifier SA at the above timing, sense amplifier SA starts to sense and amplify the potential difference between the corresponding bit lines, when the potential difference between two bit lines BL and /BL forming corresponding bit line pair increases to some extent.
As a result, the potential of bit line BL or /BL having the slightly raised potential is raised to supply potential Vcc, as indicated by solid line (1) in FIG. 8(c), in response to the rise of sense amplifier activation signal .phi.pSA (i.e., fall of sense amplifier activation signal .phi.nSA). Meanwhile, the potential of the bit line /BL or BL paired with the above bit line is lowered to ground potential Vss, as indicated by dashed line(3), in response to the rise of sense amplifier activation signal .phi.pSA (i.e., fall of sense amplifier activation signal .phi.nSA).
Conversely, the potential of bit line BL or /BL having the slightly lowered potential is lowered to ground potential Vss, as indicated by solid line (2) in FIG. 8(c), in response to the fall of sense amplifier activation signal .phi.nSA (i.e., rise of sense amplifier activation signal .phi.pSA). Meanwhile, the potential of bit line /BL or BL paired with the above bit line is raised to supply potential Vcc from intermediate potential Vb1, as indicated by dashed line (4), in response to the fall of sense amplifier activation signal .phi.nSA (i.e., rise of sense amplifier activation signal .phi.pSA).
In this manner, each bit line pair BL and /BL have the potentials at the complementary logical levels which depend on the stored data in corresponding one among a plurality of memory cells MC connected to selected word line WL.
However, only the potentials appearing on the selected bit line pair are transmitted to data line pair IO and /IO through transistors 500 and 510. For this purpose, the potential of only one of column selecting lines CSL is raised to supply potential Vcc, as shown in FIG. 8(f), after the activation of sense amplifier SA, and thus transistors 500 and 510 provided between corresponding bit line pair BL and /BL and data line pair IO and /IO are turned on.
In this manner, the complementary potentials which correspond to the stored data in one memory cell MC connected commonly to selected word line WL and selected bit line BL or /BL are transmitted to data line pair IO and /IO. The potentials transmitted to data line pair IO and /IO are externally supplied therefrom as the read data.
In the above data reading operation, the charges move between capacitor 200 in the selected memory cell MC and bit line BL or /BL connected to the selected memory cell, which causes rising or lowering of potential of node N1 or N2 in sense amplifier SA connected to this bit line. This rising or lowering to the sufficient extent requires a time of about 10 ns. Thus, it requires a considerable time until the potential difference corresponding to the stored data in selected memory cell MC is sufficiently generated between inputs N1 and N2 of sense amplifier SA connected to selected bit line pair.
Sense amplifier SA operates to sense the potential difference between its inputs N1 and N2, i.e., potential difference between corresponding bit lines BL and /BL. If this potential difference is small, the sense amplifier SA may malfunction to raise the potential of the bit line which should be lowered to ground potential Vss or to lower the potential of the bit line which should be raised to supply potential Vcc. Therefore, if sense amplifier SA is activated immediately after the rising of potential of one of word lines WL, sense amplifier SA connected to the selected bit line pair starts to operate, before the sufficient potential difference is generated between selected bit lines BL and /BL in accordance with the stored data in selected memory cell MC. Thus, sense amplifier SA may malfunction to incorrectly determine the stored data in selected memory cell MC.
In order to prevent the incorrect determination of sense amplifier SA, sense amplifier SA is activated when a certain time elapses after the rise of potential of one word line WL, i.e., when the potential difference caused by the stored data in the selected memory cell MC between selected bit lines BL and /BL increases to some extent. A waiting time is required after the rise of potential of one word line WL and before the activation of sense amplifier SA. In order to reliably prevent the malfunction of sense amplifier SA, this waiting time is set slightly longer than a time which is required after the rise of potential of one word line WL and before the potential difference between the selected bit lines BL and /BL reaches the maximum value corresponding to the capacity of the capacitor 200 in selected memory cell MC.
Therefore, even if the potential difference corresponding to the stored data in selected memory cell MC is generated between selected bit lines BL and /BL before sense amplifier SA is activated, the time is not reduced, which is after the selection of one word line WL and before the complementary potentials corresponding to the stored data in selected memory cell MC appear in data line pair IO and /IO. Consequently, it is impossible to increase the speed of the data reading operation in the conventional DRAM.
There has been proposed a DRAM, of which data reading operation does not require a time margin between the start of operation of the sense amplifier for determining the stored data in the selected memory cell and the rise of potential of one word line, e.g., by Y. Nakagome et al, "Symposium on VLSI Circuits, Dig of Tech. Papers", pp 17-18, 1990, and M. Taguchi et al, "1991 IEEE International Solid-State Circuits Conference", pp 112-113.
FIG. 9 is a circuit diagram showing a construction of a major part of such DRAM.
A DRAM shown in FIG. 9 is different from the conventional DRAM shown in FIG. 7 in that a data line pair WDB and /WDB for receiving the write data is provided independently from a data line pair RDB and /RDB for receiving the read data and that a sense amplifier RSA for amplifying the potential difference between the selected bit lines BL and /BL in the data reading operation is provided independently from sense amplifiers WSA for latching the complementary potentials corresponding to the write data in the data writing operation.
Further, read data input circuits RD are provided correspondingly to respective bit line pairs for transmitting the variation of potentials of the bit line pairs BL and /BL to read sense amplifier RSA. Also, transistors 600 and 610 for write selection are provided correspondingly to each bit line pair for interrupting flow of unnecessary current between each bit line pair BL and /BL and write data line pair WDB and /WDB.
Now, circuit operations of this DRAM for writing and reading the data will be described below with reference to FIG. 10.
FIG. 10 is a timing chart showing variation of potentials appearing on some signal lines in the circuitry in FIG. 9 in the data writing operation and data reading operation.
First, the circuit operation for reading the data will be described below.
In the data reading operation, write data line pair WDB and /WDB receives the complementary potentials, as the write data.
Write data line WDB is connected through transistors 500 and 600 to bit line BL, and write data line /WDB is connected through transistors 510 and 610 to bit line /BL paired with bit line BL. Write selection transistors 600 and 610 have gates to which a write selection signal .phi.WS is commonly applied. In the operation for writing the data in memory cell array block MA, write selection signal .phi.WS is raised to supply potential Vcc as shown in FIG. 10(h), so that all the write selection transistors 600 and 610 are turned on. Therefore, in response to the rise of potential of one column selecting line CSL, the potentials of write data lines WDB and /WDB are transmitted to selected bit lines BL and /BL, respectively.
A circuit which forms write sense amplifier WSA and has the same construction as sense amplifier SA in FIG. 7 is disposed between two bit lines BL and /BL forming each bit line pair. Therefore, the potentials transmitted to selected bit lines BL and /BL are latched at nodes N1 and N2 in corresponding write sense amplifier WSA, respectively.
If the memory cell MC connected to selected word line WL is connected to bit line BL, the data is written in selected memory cell MC in accordance with the potential latched at node N1. If the memory cell MC connected to selected word line WL is connected to bit line /BL, the data is written in selected memory cell MC in accordance with the potential latched at node N2.
As described above, this DRAM performs the data writing operation in a manner similar to the conventional circuit operation.
The circuit operation for reading the data will be described below.
In all the memory cell array blocks, write selection signal .phi.WS is at the ground potential Vss, as shown in FIG. 10(h). Thus, all write selection transistors 600 and 610 are turned off to electrically isolate bit lines BL and /BL and write data lines WDB and /WDB from each other. Therefore, when the potential (FIG. 10(b)) of one of word lines WL rises after the fall of bit line equalization signal .phi.EQ (FIG. 10(a)), the potential of each bit line BL or /BL slightly rises or lowers from the potential Vb1 in response, which it has held, on the principle similar to that of the prior art, as shown in FIG. 10(c).
Meanwhile, the potential of one column selecting line CSL is raised, as shown in FIG. 10(f), at the substantially same timing as the rise of potential of one word line WL. In this DRAM, each column selecting line CSL is connected not only to the gates of bit line selection transistors 500 and 510 but also to corresponding read data input circuit RD.
Each read data input circuit RD includes N-channel MOS transistors 700 and 710 having gates respectively connected to corresponding bit lines BL and /BL and N-channel MOS transistors 720 and 730 each having a gate connected to corresponding column selecting line CSL.
Transistors 700 and 720 are connected in series between the ground GND and read data line RDB. Transistors 710 and 730 are connected in series between the ground GND and read data line /RDB.
Accordingly, at the time that the difference potential corresponding to the stored data in selected memory cell MC starts to generate between selected bit lines BL and /BL, transistors 700 and 710 of which gates are connected to these bit lines, respectively, have already been electrically connected to read data line pair RDB and /RDB.
Read sense amplifier RSA includes P-channel MOS transistors 740 and 760 connected in series between read data line RDB and power supply Vcc, and a P-channel MOS transistor 750. Transistor 750 is connected between read data line /RDB and transistor 760. Transistors 740 and 750 have gates commonly connected to read data line RDB. Thus, read sense amplifier RSA operates to amplify the potential difference between read data lines RDB and /RDB while read sense amplifier activation signal .phi.RSA applied to the gate of transistor 760 is at the low level. Meanwhile, the elements 740, 750, 760, 700, 710, 720 and 730 serve as a current mirror.
Read sense amplifier activation signal .phi.RSA falls to the low level, as shown in FIG. 10(g), at substantially the same timing as the rise of potential of one word line WL. Therefore, when the potential difference corresponding to the stored data in selected memory cell MC starts to be generated between selected bit lines BL and /BL, read sense amplifier RSA is already activated, and is electrically connected to transistors 700 and 710 connected to selected bit lines BL and /BL.
Therefore, upon generation of the potential difference between the selected bit lines BL and /BL, the difference of the voltages applied to the transistors 700 and 710 causes difference of the currents taken out from the transistors 700 and 710, in read data input circuit RD connected to these bit lines. On the other hand, since transistors 740 and 750 have respective gates connected together, a big potential difference appears between read data lines RDB and /RDB due to the difference between a current flowing through the transistors 700 and 720 and a current flowing through the transistors 710 and 730.
If the bit line BL has a higher potential as compared with the bit line /BL, the potential on the read data line /RDB swings to a low level while the potential on the read data line RDB swings to a high level, since the transistor 700 has a larger current driving capability than the transistor 710.
Conversely, if the line BL has a lower potential as compared with the line /BL, the potential on the line RDB swings to a low level while the potential on the line /RDB swings to a high level, since the transistor 710 has a larger current driving capability than the transistor 700.
As described in the foregoing, a current mirror amplifier comprising a read sense amplifier RSA and a read data input circuit RD is responsive to a very small potential difference appearing in bit line pair immediately after rising of the potential on a word line, to amplify the potential difference and provide a big potential difference to the read data lines RDB and /RDB.
Also in the data reading operation, write sense amplifier WSA is activated at the same timing as the sense amplifier SA in FIG. 7. Thus, sense amplifier activation signals .phi.pSA and .phi.nSA go to supply potential Vcc and the ground potential Vss (see FIGS. 10(d) and 10(e)) with a considerable delay after the rise of one word line WL. Thereby, write sense amplifier WSA operates when the potential difference corresponding to stored data in selected memory cell MC sufficiently generates between selected bit lines BL and /BL.
When the sense amplifier WSA starts to operate, the potential difference between selected bit lines BL and /BL increases, so that transistor 700 or 710 in read data input circuit RD connected to bit lines BL and /BL goes to more strongly turned-on state, which increases the current flowing from read data line RDB or /RDB. Consequently, read sense amplifier RSA operates more accurately. The sense amplifier WSA is activated in order to rewrite the data of a memory cell.
In the DRAM, as described above, the variation of potentials appeared on selected bit lines BL and /BL is transmitted through the gates of transistors 700 and 710 to read sense amplifier RSA. Therefore, even if read sense amplifier RSA malfunctions due to the small potential difference between selected bit lines BL and /BL and thus the potentials of read data lines RDB and /RDB start to change contrary to the stored data in selected memory cell MC, the potentials of selected bit lines BL and /BL are not affected by incorrect variation of the potentials of the read data lines RDB and /RDB. Thus, the data read from selected memory cell MC to selected bit lines BL and /BL is not broken.
By virtue of the operation of write sense amplifier WSA, the potentials of selected bit lines BL and /BL reliably attain to the values corresponding to the stored data in selected memory cell MC. When potential difference between the selected bit lines BL and /BL is sufficiently increased owing to the operation of write sense amplifier WSA, the operation is accurately performed to set the potentials of write data lines RDB and /RDB at values corresponding to the potential difference between selected bit lines BL and /BL.
Therefore, the potentials of read data lines RDB and /RDB reliably attain to the values corresponding to the stored data in selected memory cell MC, even if the time of start of the operation of read sense amplifier RSA is not delayed from the time of rise of potential of word line WL.
Conversely, if sense amplifier SA in FIG. 7 malfunctions in the data reading operation, the potentials themselves of selected bit lines BL and /BL do not reflect the stored data in selected memory cell MC, so that incorrect data ultimately appears on data lines IO and /IO. In addition, the data in the memory cell which should be rewritten correctly is damaged, which is a big problem.
In the data reading and writing operations, bit line selection transistors 500 and 510 which are provided correspondingly to selected bit lines BL and /BL, respectively, are turned on. Therefore, selected bit lines BL and /BL would be electrically connected by corresponding bit line selection transistors 500 and 510 to write data lines WDB and /WDB, respectively, if write selection transistors 600 and 610 do not exist. Meanwhile, write data lines WDB and /WDB are fixed at supply potential Vcc or the ground potential Vss in the operations other than that for writing the data in corresponding memory cell array block MA.
Generally, the DRAM includes a plurality of memory cell array blocks MA, and a plurality of write data line pairs WDB and /WDB are provided correspondingly to them.
FIG. 11 is a schematic block diagram showing a whole construction of a DRAM in which write data line pairs WDB and /WDB are provided independently from read data line pairs RDB and /RDB.
With reference to FIG. 11, when a plurality of memory cell array blocks MA are disposed in a column direction, for each memory cell array block MA, there are provided write data line pair WDB and /WDB and write sense amplifier WSA connected to bit line pairs BL and /BL in the memory cell array block as well as one read data line pair RDB and /RDB, read data input circuit RD connected to bit line pairs BL and /BL in memory cell array block and one read sense amplifier RSA.
Column selecting lines CSL are provided commonly to memory cell array blocks MA. Thus, memory cell array blocks MA include the same number of columns of memory cells. Gates of transistors 500 and 510 as well as transistors 720 and 730, which are connected to bit line pair corresponding to the same column, are commonly connected to the same column selecting line CSL.
In the data writing and reading operations, column decoder CD selectively applies the potential at the high level to one of column selecting lines CSL. Therefore, in the data reading and writing operations, the potential at the high level is applied to one of the column selecting lines CSL in each memory cell array block MA.
Word lines WL, however, are provided independently in respective memory cell array blocks MA. In the data reading and writing operations, row decoder RDE supplies a potential (Vcc+.alpha.) slightly higher than supply potential Vcc to one of the word lines WL in any one of the memory cell arrays MA. Therefore, both the potentials of one column selecting line CSL and one word line WL go to the high level only in one memory cell array block MA. Consequently, the data is written in and read from selected memory cells MC only in this one memory cell array block MA.
Each write data line pair WDB and /WDB is electrically connected to a common write data line pair GWDB and /GWDB only while corresponding memory cell array MA is selected. In the data writing operation, the write data, i.e., the potentials at the complementary logical levels are supplied to common write data line pair GWDB and /GWDB. These complementary potentials are applied through corresponding write data line pair WDB and /WDB only to one of the bit line pairs BL and /BL in selected memory cell array block MA, i.e., memory cell array block MA including word line WL to which the high potential is applied from row decoder RDE. More specifically, bit line pair BL and /BL to which the complementary potentials are actually applied is the bit line pair connected to one column selecting line CSL to which the potential at the high level is applied from column decoder CD.
As described above, since the memory cell array is divided into memory cell array blocks MA in the practical construction, the potential of one column selecting line CSL has the high level in not only selected memory cell array block but also each of unselected memory cell array blocks in both the data reading operation and data writing operation.
Therefore, in FIG. 9, even when memory array block MA is not selected transistors 500 and 510 connected to one of bit line pairs BL and /BL in unselected memory cell array block MA are turned on. When memory cell array block MA is not selected, write data lines WDB and /WDB which are provided correspondingly to unselected memory cell array block MA are fixed at supply potential Vcc or the ground potential Vss.
Meanwhile, each bit line pair BL and /BL in unselected memory cell array block MA is equalized by bit line equalizer circuit EQ connected thereto to an intermediate potential Vb1. Therefore, if write selection transistors 600 and 610 were not provided, current flows from a power supply feeding the intermediate potential Vb1 to the equalizer circuit EQ (hereinafter referred to as a bit line precharge power supply: not shown) to write data line WDB through the selected bit line BL and transistors 400 and 500 connected to this bit line, and current flows between bit line precharge power supply and the other write data line /WDB through the other selected bit line /BL and transistors 410 and 510 connected thereto, in each of the non-selected blocks.
As described above, if bit line selection transistors 600 and 610 were not provided, useless current would flow between the bit line precharge power supply and the power supply for supplying supply potential Vcc or the ground potential Vss to write data line pair WDB and /WDB, in each unselected block, resulting in increase of power consumption. Bit line selection transistors 600 and 610 are provided for preventing the above problem.
In the data reading and writing operations, all write selection transistors 600 and 610 which are provided correspondingly to the unselected blocks receive write selection signal .phi.WS at the low level to be turned off, so that current paths between bit lines BL and /BL and write data line pairs WDB and /WDB are interrupted in these unselected blocks, respectively. In each unselected block, therefore, the current does not flow between write data line pair WDB and /WDB and bit line precharge power supply through bit line pair BL and /BL corresponding to one column selecting line CSL to which the potential at the high level is applied.
As described above, the DRAM of a so-called separated I/O type, which is independently provided with read data line pairs and write data line pairs, requires read data input circuits RD and two write selection transistors 600 and 610 which are provided correspondingly to the respective bit line pairs. Each read data input circuit RD is formed of four transistors 700, 710, 720 and 730, as shown in FIG. 9.
Therefore, the DRAM of separated I/O type has a construction identical with the construction in which six transistors are additionally provided correspondingly to each bit line pair in a DRAM of so-called common I/O type in which read data lines and write data line pairs are common to each other (see FIG. 7).
The DRAM of separated I/O type requires a signal line for supplying selection signal .phi.WS for controlling the write selection transistors to the gates of write selection transistors 600 and 610.
Therefore, the DRAM of separated I/O type in the prior art has a large number of components, elements and signal lines, so that it occupies larger chip area than that the DRAM of common I/O type.
In order to avoid the above problem, the write selection transistors may be eliminated. In this case, however, the current flows between the bit line precharge power supply and power supply for applying Vss or Vcc through write data line pairs WDB and /WDB in the unselected blocks, on the principle described above.
Thus, it is difficult to suppress both the increase of the occupied chip area and increase of the power consumption in the conventional DRAM in which the access time in the data reading operation is reduced.